A system-on-chip (SOC) integrated circuit is a single chip or integrated circuit that includes all the necessary electronic circuitry to form a complete system. For example, an SOC integrated circuit may include on-chip memory such as random access memory (RAM), a microprocessor, a digital signal processor (DSP), a universal serial bus (USB) port, other peripheral interfaces, and other components to a complete computer system within a single integrated circuit. Such SOC integrated circuits are utilized in a variety of devices, such as digital cameras, cellular phones, and personal digital assistants (PDAs).
In an SOC integrated circuit, each of the various functional circuit blocks, such as the microprocessor and memory in the computer system example above, may be referred to as an intellectual property (IP) core. An IP core is thus a block of logic that provides required functionality and is commonly utilized in multiple integrated circuits through a process that is known as “reuse.” Thus, through reuse the same IP core may be utilized in a first SOC integrated circuit and in a different second SOC integrated circuit. Because the specific designs of the first and second SOC integrated circuits are different, and also due to the variation of semiconductor manufacturing processes for each, the IP core, as well as the other circuitry in the integrated circuit the core is embedded within, must be tested for each integrated circuit to ensure its proper operation. For example, where the IP core being tested corresponds to circuitry that implements the universal serial bus (USB) protocol, the IP core must be independently tested for each SOC integrated circuit due to the different components and layouts from one SOC integrated circuit to the next.
The IP core can be very complex, consisting of closely coupled complex analog and digital components, and consisting of multiple levels of design hierarchies. For example, the IP cores that implement high speed wired or wireless communication protocols such as USB, PC1 Express, wireless LAN, etc., typically are complex sub-systems just by themselves. Testing of this kind of IP core in a SOC integrated circuit is an expensive and difficult task. Traditional scan and BIST methods can not provide satisfactory coverage and flexibility. One prior approach for testing this kind of complex IP core in an SOC integrated circuit is to provide multiplexers for routing all required signals to and from each IP core within the integrated circuit through external pins of the SOC integrated circuit. In this way, an automated tester coupled to the SOC integrated circuit could transfer all required signals to and from each IP core to properly test that core. Such an approach is not always practical for a variety of reasons. For example, in some instances a given IP core may have more signals than there are external pins of the SOC integrated circuit. In this situation multiplexing all the required signals for the IP core through the external pins of the integrated circuit may prohibitively complicate or increase the cost of testing such an IP core. Where the SOC integrates multiple complex mixed-signal IP instances, reliable and cost effective testing will also require prohibitively complex and expensive automated testers.
There is a need for comprehensively and efficiently testing complex IP cores in SOC integrated circuits.